1. Field of the Invention
The present invention relates to data processing systems and, in particular, to passing data between two or more clock domains operating asynchronously.
2. Background Information
Due to the various speeds in which the various devices and circuits within a data processing system operate, it is desirable to provide several clock domains to accommodate for these differences in speeds. For instance, with the advancement of semiconductor architectures and manufacturing techniques, the speed of the semiconductor components, such as the processing unit, is ever increasing. However, such may not be the case with various input/output (I/O) devices that are used in the system. For instance, these devices may be connected to a Peripheral Computer Interconnect (PCI) bus that operates at 33/66 Megahertz (MHz), and in the case of the PCI-X bus, it operates at 66/100/133 MHz. The processing unit that communicates with these devices, in turn, may be operating at much higher speeds outpacing their operating speeds. In these instances, it is desirable to divide the system into several clock domains according to the clock speeds. However, there are many instances in which data is passed from one clock domain to another. Because the two clock domains are operating at independent or different speeds, it is important that data is passed from one domain to another without loss and with mininal delays.
Similar problems exist even within a semiconductor component itself. For instance, due to higher integration technologies, cost reduction benefits and/or reliability of the system, there are many instances in which multiple circuits requiring different operating clock speeds are etched onto a single piece of silicon. In other instances, the nature of the semiconductor component itself demands that the component operates in multiple clock domains. Take for example, an I/O bridge that connects one or more industry standard buses, like the PCI/PCI-X bus, to the processor or the processor bus. This I/O bridge may be divided into two sections. The first section interfaces with the processor/processor bus while the second section interfaces with the industry standard buses. It is desirable for the first section to operate at high clock frequencies that are compatible with the processor/processor bus while the second section operates at the lower clock frequencies that are compatible with the industry standard buses. This configuration allows for low latency and high data bandwidth to be maintained at the first section while multiple industry standard busses are operating simultaneously at independent frequencies that may be the same or different. However, data needs to be passed between the two sections.
There are also instances in which it is desired to operate the processing system with a deterministic behavior. Deterministic behavior is where a transaction, such as a transfer of data from an I/O device to memory, is deterministic. That is, its behavior at each cycle of a transaction can be duplicated by a similar processing system operating independently when presented with a common stimulus. However, when data is being passed between multiple asynchronous clock domains within a processing system, in particular, at high clock speeds, a synchronizer of one processing system may pass data at a different clock cycle from that passed by a synchronizer in another processing system. In these instances, the two processing systems are not operating in a deterministic manner and thus may lead to undesired consequences for applications relying on the deterministic behavior of the processing system.
One or more phase-locked loop circuits (PLLs) are used to facilitate the passing of data between multiple asynchronous domains. According to an embodiment of the invention, a first PLL (PLL-1) supplies a fast clock that is used by the circuits in the fast clock domain. The clock that feeds the PLL-1 also feeds a second PLL (PLL-2) that generates a xe2x80x9cmasterxe2x80x9d slow clock, which is used in the slow clock domain and is a ratio of frequency to the fast clock. The master slow clock is used to feed the circuits and/or one or more PLLs in the slow clock domain. For ease of explaining the invention, only one of the PLLs in the slow clock domain will be used and will be referred to as a third PLL (PLL-3). The output clock of PLL-2 is placed in a locked phase and a known clock edge relationship with the output clock of PLL-1. Further, the clock of PLL-3 is in a locked phase and a known clock edge relationship with PLL-1 because PLL-2 provides the reference clock to PLL-3. In sum, PLL-1, PLL-2 and PLL-3 are in locked phase; i.e., in a known phase and edge relationship. For data to cross the clock domains deterministically, data is allowed to cross on common clock edges, that is, when the rising edges of the fast and slow clocks coincide. This alignment is predicted by a fast clock state machine and a slow clock state machine, which generates a fast-to-slow clock domain signal and a slow-to-fast clock domain signal respectively, in which data is permitted to pass between the two clock domains.